Keithley 2948 Parallel Parametric free download

File name 2948_Parallel_Parametric.pdf

A GREAT ER M EA SU R E O F C O N F I D E N C E probe touchdown, parallel test offers fabs the flexibility to choose whether they want to increase their wafer test throughput dramati- cally, or use the available time to acquire sig- nificantly more data and thereby gain greater insight into production processes. At the present time, structures being tested in parallel are typically located within a single Test Element Group (TEG). Few IC manufacturers test structures in different TEGs simultaneously. To implement this strategy the parametric tester's controller is used to inter-leave execution of multiple tests in a way that maximizes available processing time and test instrumentation Parallel Parametric capacity, which might otherwise have idle periods. With proper test structure design,